1. Field
The embodiment relates to a data transfer control apparatus and a data transfer control method.
2. Description of the Related Art
A conventional data transfer control apparatus for performing data transfer is provided between a storage apparatus and a processing apparatus. The conventional apparatus is configured to use First-In First-Out memory (FIFO memory) as a buffer. Buffering allows for differences between the transfer rates of the storage apparatus side and the processing apparatus side.
FIG. 1 illustrates a block diagram showing the configuration of the conventional data transfer control apparatus. A write control part 1101 is provided at memory side to control the writing of write data to FIFO memory 1102. The memory may be Synchronous Dynamic Random Access Memory (SDRAM). Meanwhile, a read control part 1103 is provided at the processing apparatus side (core side) to control the reading of data (read data) which were written in FIFO memory 1102. FIFO memory 1102 has a storage capacity of 64 bits×256 words for example.
As shown in FIG. 1, an asynchronous transfer part 1104 is provided between the write control part 1101 and the read control part 1103. The asynchronous transfer part 1104 receives a notification of transfer-start and a pointer of transfer-start which are input from the write control part 1101. Then the asynchronous transfer part 1104 transfers the notification of transfer-start and the pointer of transfer-start to the read control part 1103 during clock exchange.
In the configuration of FIG. 1, the core side operating frequency is 100 MHz, the amount of read data which is read at the core side per cycle is 64 bits, the memory side operating frequency is 200 MHz, and the amount of write data which is written at the memory side per cycle is 64 bits. In the above-described configuration, the read rate at the core side is 64 bits/100 MHz=800 Mbyte/sec, and the write rate at the memory side is 64 bits/200 MHz=1600 Mbyte/sec. The read rate of 800 Mbyte/sec is less than the write rate of 1600 Mbyte/sec. If the read-start is notified to the core simultaneously with the write-start by the memory side, reading operation at the core side does not overtake writing operation at the memory side. It is assumed that the writing operation at the memory side is performed without interruption.
In the conventional data transfer control apparatus of FIG. 1, the reading operation at the core side which starts before writing to FIFO memory 1102 is complete in order to improve data transfer efficiency. The reading operation at the core side overtakes the writing operation at the memory side if the read rate is greater than the write rate when the above-described transfer control is performed, depending on the timing when the reading operation at the core side starts.
For example, in the configuration of FIG. 1, the core side operating frequency is 100 MHz, the amount of read data which is read at the core side per cycle is 64 bits, the memory side operating frequency is 200 MHz, and the amount of write data which is written at the memory side per cycle is 16 bits. Thus, the read rate 800 Mbyte/sec is greater than the write rate 400 Mbyte/sec. If the read rate is greater than the write rate, the reading operation at the core side overtakes the writing operation at the memory side and valid data is corrupted when the writing operation at memory side and the reading operation at the core side are performed simultaneously. Conversely, if the reading operation at the core side starts in order to prevent the corruption of valid data after all the writing operation at the memory side is completed, time is wasted and the data transfer efficiency is reduced.
There is a problem that the reading operation overtakes the writing operation and the data transfer efficiency is reduced in the aforementioned conventional data transfer control apparatus.